Yamuna Rajasekhar, Ph. D.

Research Highlights

  • Reconfigurable computing
  • High performance computing
  • Embedded Systems
  • Computer architecture
  • Memory systems
Portrait of Yamuna Rajaskhar

Assistant Professor

260 D Garland Hall
513-529-0744
rajasey@MiamiOH.edu

Degrees

  • Ph.D.Electrical Engineering, University of North Carolina at Charlotte2014
  • M.S.Electrical Engineering, University of North Carolina at Charlotte—2008
  • B.S.Electronics and Telecommunication Engineering, University of Mumbai, India2006

Experience

  • Assistant Professor, Miami University, 2015present
  • Instructor, UNC Charlotte, 20142015
  • Graduate Research Assistant, UNC Charlotte, 20112014
  • Visiting Research Scientist, Information Sciences Institute, VA, 2011

Honors and Awards

  • Graduate Life Fellowship Recipient, 20132014
  • Graduate Research Fair Winner, 2008 (Category: Engineering)

Principal Publications

  • Yamuna Rajasekhar and Ron Sass. A Novel Memory Subsystem and Computational Model for Parallel Reconfigurable Architectures. in Euro-Par 2013: On-chip Memory Hierarchies and Interconnects (Springer).
  • Yamuna Rajasekhar and Ron Sass. Architecture and Applications for an All-FPGA Parallel Computer. In Cluster Computing, 2013
  • Rahul R. Sharma, Yamuna Rajasekhar and Ron Sass. Exploring Hardware Work Queue Support for Lightweight Threads in MPSoCs. In proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), December 2012
  • Yamuna Rajasekhar and Ron Sass. Architecture and Applications for an All-FPGA Parallel Computer. In proceedings of the 41st International Conference on Parallel Processing Workshops (ICPP’2012), September 2012
  • Yamuna Rajasekhar, Rahul R. Sharma and Ron Sass. An Extensible and Portable Tool Suite for Managing Multi-Node FPGA Systems. In Proceedings of the 20th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’12). IEEE Computer Society, April 2012
  • William V. Kritikos and Yamuna Rajasekhar and Andrew G. Schmidt and Ron Sass. A Radix Tree Router for Scalable FPGA Networks. In 21st Annual Conference on Field Programmable Logic and Applications (FPL’11). IEEE Computer Society, September 2011
  • Yamuna Rajasekhar and Ron Sass. A First Analysis of a Dynamic Memory Allocation Controller (DMAC) Core. In proceedings of the Symposium on Application Accelerators in High-Performance Computing, June 2011
  • Yamuna Rajasekhar, William V. Kritikos, Andrew G. Schmidt, and Ron Sass. Teaching FPGA System Design via a Remote Laboratory Facility. In 18th Annual Conference on Field Programmable Logic and Applications (FPL’08). IEEE Computer Society, September 2008.
  • Yamuna Rajasekhar, Yashodhan Phatak, Andrew G. Schmidt, William V. Kritikos, and Ron Sass. FPGA Session Control (FSC): Providing Remote Access to A Cluster of FPGAs. In Proceedings of the 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’08). IEEE Computer Society, April 2008.